Data transmission is an important aspect of integrated circuit devices. A continuous time linear equalizer (CTLE) may be necessary to receive data, particularly high speed data. Existing CTLE designs for high frequency equalization relies on degeneration resistance to change the amount of relative high-frequency boost. For higher loss channels, more equalization is needed. However, with a conventional CTLE design, the amplitude of the signal is heavily attenuated. In many cases, the signal is already small for high loss channels. This loss in amplitude has to be compensated in a conventional device by requiring more gain from a following Automatic Gain Control (AGC) stage. However, the additional gain requirement in the AGC stage can consume additional power, which is not desirable.
Accordingly, circuits and methods that reduce power when implementing a CTLE are beneficial.